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9212g-auto-09/13 features pwm and direction-controlled driving of four externally-powered nmos transistors high temperature capability up to 200c junction a programmable dead time is included to avoid peak currents within the h-bridge integrated charge pump to provide gate vo ltages for high-side drivers and to supply the gate of the external battery reverse protection nmos 5v/3.3v regulator and current limitation function reset derived from 5v/3.3v regulator output voltage a programmable window watchdog battery overvoltage protection and battery undervoltage management overtemperature warning and protection (shutdown) high voltage serial interface for communication tpqfp package description the atmel ? ATA6824C is designed for dc motor control application in automotive high temperature environment like in mechatronic assemblies in the vicinity of the hot engine, e.g. turbo charger. with a maximum junction temperature of 200c, atmel ATA6824C is suitable for applications with an ambient temperature up to 150c. the ic includes 4 driver stages to control 4 external power mosfets. an external micro- controller provides the direction signal and the pwm frequency. in pwm operation, the high-side switches are permanently on while the low-side switches are activated by the pwm frequency. atmel ATA6824C contains a voltage regulator to supply the microcon- troller; via the input pin vmode the output volt age can be set to 5v or 3.3v respectively. the on-chip window watchdog timer provides a pin-programmable time window. the watchdog is internally trimmed to an accuracy of 10%. for communication a high voltage serial interface with a maximum data range of 20kbaud is integrated. ATA6824C high temperature h-bridge motor driver datasheet
ATA6824C [datasheet] 9212g?auto?09/13 2 figure 1. block diagram vmode /reset microcontroller logic control vcc tp2 wd 12v regulator vint 5v regulator otp 12 bit oscillator vcc 5v regulator bandgap charge pump hs driver 2 vres h2 cp cp cplo vbatsw vbat vbat battery vbg pbat vint vg cpih h1 m s1 s2 l2 vbat gnd dg3 tp1 sio cc dg2 pgnd l1 ot uv ov hs driver 1 r gate r gate r gate r gate ls driver 2 supervisor cc timer wd timer serial interface ls driver 1 dir tx rx pwm dg1 c vres c cp c vg c vint c vcc c cc r cc r rwd c sio
3 ATA6824C [datasheet] 9212g?auto?09/13 1. pin configuration figure 1-1. pinning tpqfp32 note: yww date code (y = year - above 2000, ww = week number) ATA6824C product name zzzzz wafer lot number al assembly sub-lot number table 1-1. pin description pin symbol i/o function 1 vmode i selector for v cc and interface logic voltage level 2 vint i/o blocking capacitor 220nf/10v/x7r 3 rwd i resistor defining the watchdog interval 4 cc i/o rc combination to adjust cross conduction time 5 /reset o reset signal for microcontroller 6 wd i watchdog trigger signal 7 gnd i ground for chip core 8 sio i/o high voltage (hv) serial interface 9 tx i transmit signal to serial in terface from microcontroller 10 dir i defines the rotation direction for the motor 11 pwm i pwm input controls motor speed 12 tp1 ? test pin to be connected to gnd 13 rx o receive signal from serial interface for microcontroller 14 dg3 o diagnostic output 3 15 dg2 o diagnostic output 2 16 dg1 o diagnostic output 1 17 s1 i/o source voltage h-bridge, high-side 1 18 h1 o gate voltage h-bridge, high-side 1 19 s2 i/o source voltage h-bridge, high-side 2 20 h2 o gate voltage h-bridge, high-side 2 21 vres i/o gate voltage for reverse protection nmos, blocking capacitor 470nf/25v/x7r 22 cphi i charge pump capacitor 220nf/25v/x7r 23 cplo o vmode vint rwd cc /reset wd gnd sio vg cplo cphi vres h2 s2 h1 s1 tp2 vbatsw vbat vcc pgnd l1 l2 pbat tx dir pwm tp1 rx dg3 dg2 dg1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 atmel yww ata6824 zzzzz-al
ATA6824C [datasheet] 9212g?auto?09/13 4 2. general statement and conventions parameter values given without tolerances are indi cative only and not to be tested in production parameters given with tolerances but without a paramete r number in the first column of parameter table are ?guaranteed by design? (mainly covered by measurement of other s pecified parameters). thes e parameters are not to be tested in production. the tolerances are given if the knowledge of the para meter tolerances is important for the application the lowest power supply voltage is named gnd all voltage specifications are refe rred to gnd if not otherwise stated sinking current means that the current is flowing into the pin (value is positive) sourcing current means that the current is flowing out of the pin (value is negative) 2.1 related documents qualification of integrated ci rcuits according to atmel ? hno procedure based on aec-q100 aec-q100-004 and jesd78 (latch-up) esd stm 5.1-1998 cei 801-2 (only for information regarding esd requirements of the pcb) 24 vg i/o blocking capacitor 470nf/25v/x7r 25 pbat i power supply (after reverse protection) for charge pump and h-bridge 26 l2 o gate voltage h-bridge, low-side 2 27 l1 o gate voltage h-bridge, low-side 1 28 pgnd i power ground for h-bridge and charge pump 29 vcc o 5v/100 ma supply for microcontroller, blocking capacitor 2.2f/10v/x7r 30 vbat i supply voltage for ic core (after reverse protection) 31 vbatsw o 100 ? pmos switch from v vbat 32 tp2 ? test pin to be connected to gnd table 1-1. pin description (continued) pin symbol i/o function
5 ATA6824C [datasheet] 9212g?auto?09/13 3. application 3.1 general remark this chapter describes the principal application for which the atmel ? ATA6824C was designed. because atmel cannot be considered to understand fully all aspects of the system, applic ation and environment, no warranties of fitness for a particula r purpose are given. 4. functional description 4.1 power supply unit with supervisor functions 4.1.1 power supply the ic is supplied by a reverse-protected battery voltage. to prevent it from destruction, prope r external protection circuitry has to be added. it is recommended to use at least a capaci tor combination of storage and hf caps behind the reverse protection circuitry and closed to the vbat pin of the ic (see figure 1 on page 2 ). an internal low-power and low drop regulator (v int ), stabilized by an external blocking capacitor, provides the necessary low- voltage supply for all internal blocks except the digital io pins . this voltage is also needed in the wake-up process. the low- power band gap reference is trimmed and is used for the bigger v cc regulator, too. all internal blocks are supplied by the internal regulator. the internal supply voltage v int must not be used for any other supply purpose! nothing inside the ic except the logic interface to the microcontroller is supplied by the 5v/3.3v vcc regulator. a power-good comparator checks the output volt age of the v int regulator and keeps the whole chip in reset as long as the voltage is too low. there is a high-voltage switch which bri ngs out the battery voltage to the pin vbatsw for measurement purposes. this switch is switched on for vcc = high and stays on in case of a watchdog reset. the signal can be used to switch on external voltage regulators, etc. table 3-1. typical external components (see also figure 1 on page 2 ) component function value tolerance c vint blocking capacitor at vint 220nf, 10v, x7r 50% c vcc blocking capacitor at vcc 2.2f, 10v, x7r 50% c cc cross conduction time definition capacitor typical 680pf, 100v, cog r cc cross conduction time definition resistor typical 10k ? c vg blocking capacitor at vg typical 470nf, 25v, x7r 50% c cp charge pump capacitor typical 220nf, 25v, x7r c vres reservoir capacitor typical 470nf, 25v, x7r r rwd watchdog time definition resistor typical 51k ? c sio filter capacitor for sio typical 220pf, 100v
ATA6824C [datasheet] 9212g?auto?09/13 6 4.1.2 voltage supervisor this block is intended to protect the ic and the external powe r mos transistors against overvo ltage on battery level and to manage undervoltage on it. function: in case of both overvoltage alarm (v thov ) and of undervoltage alarm (v thuv ) the external nmos motor bridge transistors will be switched off. the failure state will be flagged via dg2. no other actions will be carried out. the undervoltage comparator is connected to th e pin vbat while the overvoltage comparat or is connected to pin pbat. both are filtered by a first-order low pass with a corner frequency of typical 15khz. 4.1.3 temperature supervisor there is a temperature sensor integrated on-chip to prevent the ic from overheating due to a failure in the external circuitry and to protect the external nmosfet transistors. in case of detected overtemperature (180c) , the diagnostic pin dg3 will be switched to ? h? to signalize overtemperature warning to the microcontroller. it should undertake actions to reduce the power dissipation in the ic. in case of detected overtemperature (200c), the v cc regulator and all drivers including the seri al interface will be switched off immediately and /reset will go low. both temperature thresholds are correlated. the absolute toleranc e is 15k and there is a built-in hysteresis of about 10k to avoid fast oscillations. after cooling down below the 170c threshold; the ic will go into active mode. the occurrence of overtemperature sh utdown is latched in dg3. dg3 stays on high until first wd trigger. 4.2 5v/3.3v vcc regulator the 5v/3.3v regulator is fully integrated on-chip. it requ ires only a 2.2f ceramic capacit or for stability and has 100 ma current capability. using the vmod e pin, the output voltage can be selected to either 5v or 3.3v. switching of the output voltage during operation is not intended to be supported. the vmode pin must be hard-wired to either vint for 5v or to gnd for 3.3v. the logic high level of the microcontroller interface will be adapted to the vcc regulator voltage. the output voltage accuracy is in ge neral < 3%; in the 5v mode with v vbat < 9v it is limited to < 5%. to prevent destruction of the ic, the current delivered by the regulato r is limited to maximum 100ma to 350ma. the delivered voltage will break down and a reset may occur. please note that this regulator is the ma in heat source on the chip. the maximum output current at maximum battery voltage and high ambient temperature can onl y guaranteed if the ic is moun ted on an efficient heat sink. a power-good comparator checks the output voltage of the vcc re gulator and keeps the external microcontroller in reset as long as the voltage is too low. figure 4-1. voltage de pendence and timing of vcc controlled reset t res t delayresl v thres 5v vcc /reset
7 ATA6824C [datasheet] 9212g?auto?09/13 figure 4-2. correlation between vcc output voltage and reset threshold the voltage difference between the regulator output voltage and the upper reset threshold voltage is bigger than 75mv (vmode = high) and bigger t han 50mv (vmode = low). 4.3 reset and watchdog management the timing basis of the watchdog is provided by the trimmed internal oscillator. its period t osc is adjustable via the external resistor r wd . the watchdog expects a triggering signal (a rising edge) from the microcontroller at the wd input within a period time window of t wd . figure 4-3. timing diagram of the watchdog function v cc1 v cc1-vthresh = v cc1 - v thresh v thresh 5.15v vcc tracking voltage vcc1-thresh 4.9v 4.85v 4.1v t res t d t d t 1 t 2 t 1 t 2 t resshort /reset wd
ATA6824C [datasheet] 9212g?auto?09/13 8 4.3.1 timing sequence for example, with an external resistor r wd =33k ? 1% we get the following typical parameters of the watchdog. t osc = 12.32s, t 1 = 12.1ms, t 2 = 9.61ms, t wd = 16.88ms 10% the times t res = 70ms and t d = 70ms are fixed values with a tolerance of 10%. after ramp-up of the battery voltage (power-on reset), the v cc regulator is switched on. th e reset output, /reset, stays low for the time t res , then switches to high. for an initial lead time t d (for setups in the controller) the watchdog waits for a rising edge on wd to start its normal window watchdog sequence. if no rising edge is detected, the watchdog will reset the microcontroller for t res and wait t d for the rising edge on wd. times t 1 (close window) and t 2 (open window) form the window watchdog sequence. to avoid receiving a reset from the watchdog, the triggering signal from the mi crocontroller must hit the timeframe of t 2 = 9.61ms. the trigger event will restart the watchdog sequence. figure 4-4. t wd versus r wd if triggering fails, /reset will be pulled to ground for a shorten ed reset time of typically 2ms. the watchdog start sequence is similar to the power-on reset. the internal oscillator is trimmed to a tolerance of < 10%. this means that t 1 and t 2 can also vary by 10%. the following calculation shows the worst case ca lculation of the watchdog period t wd which the microcontroller has to provide. t 1min = 0.90 ? t 1 = 10.87ms, t 1max = 1.10 ? t 1 = 13.28ms t 2min = 0.90 ? t 2 = 8.65ms, t 2max = 1.10 ? t 2 = 10.57ms t wdmax = t 1min + t 2min = 10.87ms + 8.65ms = 19.52ms t wdmin = t 1max = 13.28ms t wd = 16.42ms 3.15ms (19.1%) figure 4-4 on page 8 shows the typical watchdog period t wd depending on the value of the external resistor r osc . a reset will be active for v cc < v thresx ; the level v thresx is realized with a hysteresis (hys resth ). rwd (k) 0 0 2030405060708090100 10 20 30 40 50 60 twd (ms) max min typ
9 ATA6824C [datasheet] 9212g?auto?09/13 4.4 high voltage serial interface a bi-directional bus interface is implem ented for data transfer between hostcontroll er and the local microcontroller (sio). the transceiver consists of a low side driver (1.2v at 40ma) wit h slew rate control, wave shap ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. 4.4.1 transmit mode during transmission, the data at the pin tx will be transferred to the bus driver to generate a bus signal on pin sio. the pin tx has a pull-down resistor included. to minimize the electromagnetic emission of the bus line, t he bus driver has an integrated slew rate control and wave- shaping unit. in transmit mode, transmission will be inte rrupted in case of overheating at the sio driver. 4.4.2 reset mode in case of an active reset shown at pin /reset the pin sio is switched to low, indepen dent of the temperature. the maximum current is limited to i sio_lim_reset . figure 4-5. definition of bus timing parameters the recessive bus level is generated from the integrated 30 k ? pull-up resistor in series with an active diode. this diode prevents the reverse current of vbus durin g differential voltage between vsup and bus (v bus >v sup ). t bit th rec(min) th dom(min) th rec(max) thresholds of receiving node 2 thresholds of receiving node 1 th dom(max) t sio_dom(max) t sio_rec(min) t sio_dom(min) t rx_pdr(2) t rx_pdf(2) t rx_pdf(1) t rx_pdr(1) t sio_rec(max) t bit t bit v vbat (transceiver supply of transmitting node) rx (output of receiving node 2) rx (output of receiving node 1) tx sio signal (input to transmitting node)
ATA6824C [datasheet] 9212g?auto?09/13 10 4.5 control inputs dir and pwm 4.5.1 pin dir logical input to control the direction of the external motor to be controlled by the ic. an internal pull-down resistor is included. 4.5.2 pin pwm logical input for pwm information delivered by external micr ocontroller. duty cycle and frequency at this pin are passed through to the h-bridge. an inter nal pull-down resistor is included. the internal signal on is high when at least one valid wd trigger has been accepted no short circuit detected v pbat is inside the specified range (v pbat_ov v pbat v thov ) v vbat is higher than v thuv the device temperature is not above shutdown threshold in case of a short circuit, the appropriate trans istor is switched off after a blanking time of t sc . in order to avoid cross current through the bridge, a cross conduction timer is implemented. its time constant is progr ammable by means of an rc combination. table 4-1. status of the ic depending on control inputs and detected failures control inputs driver stage for external power mos comments on dir pwm h1 l1 h2 l2 0 x x off off off off dg1, dg2 fault or reset 1 0 pwm on off /pwm pwm motor pwm forward 1 1 pwm /pwm pwm on off motor pwm reverse table 4-2. status of the diagnostic outputs device status diagnostic outputs comments pbat_uv sc vbat_uv pbat_ov cpok ot dg1 dg2 dg3 x x x x x 1 ? ? 1 overtemperature warning x x x x 0 x 0 1 ? charge pump failure x x x 1 x x 0 1 ? overvoltage pbat x x 1 x x x 0 1 ? undervoltage vbat x 1 0 0 1 x 1 0 ? short circuit 1 0 0 0 1 x 1 1 ? undervoltage pbat note: x represents: don?t care ? no effect) pbat_uv: undervoltage pbat pin sc: short circuit drain source monitoring vbat_uv: undervoltage of vbat pin pbat_ov: overvoltage of pbat pin cpok: charge pump ok ot: overtemperature warning ? status of the diagnostic ou tputs depends on device status
11 ATA6824C [datasheet] 9212g?auto?09/13 4.6 vg regulator the vg regulator is used to generate the ga te voltage for the low-side driver. its out put voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. the purpose of the regulator is to limit the gate voltage for the external power mos transistors to 12v. it needs a ceramic capacitor of 470nf for stability. the output voltage is reduced if the supply vo ltage at vbat falls below 12v. 4.7 charge pump the integrated charge pump is needed to supply the gates of the external power mos transistors. it needs a shuffle capacitor of 220nf and a reservoir capacit or of 470nf. without load, the output voltage on the reservoir capacitor is v vbat plus vg. the charge pump is clocked with a dedicated internal oscillator of 100khz. the charge pump is designed to reach a good emc level. the charge pump will be switched off for v vbat > v thov . 4.8 thermal shutdown there is a thermal shutdown block implemented. with rising ju nction temperature, a first wa rning level will be reached at 180c. at this point the ic stays fully fu nctional and a warning will be sent to the mi crocontroller. at junction temperature 200c the drivers for h1, h2, l1, l2, sio and the vcc regulator will be switched off and a reset occurs. 4.9 h-bridge driver the ic includes two push-pull drivers for control of two extern al power nmos used as high-side drivers and two push-pull drivers for control of two external power nmos used as low-si de drivers. the drivers are able to be used with standard and logic-level power nmos. the drivers for the high-side control use the charge pump voltage to supply the gates with a vo ltage of vg above the battery voltage level. the low-side drivers are supplied by vg directly . it is possible to control the external load (motor) in the forward and reverse direction (see table 4-1 on page 10 ). the duty cycle of the pmw cont rols the speed. a duty cycle of 100% is possible in both directions. 4.9.1 cross conduction time to prevent high peak currents in the h-bridge, a non-overlappi ng phase for switching the external power nmos is realized. an external rc combination defines the cross conduction time in the following way: t cc (s) = 0.41 ? r cc (k ? ) ? c cc (nf) (tolerance: 5% 0.15s) the rc combination is charged to 5v and the switching leve l of the internal comparator is 67% of the start level. the resistor r cc must be greater than 5k ? and should be as close as possible to 10k ? , the c cc value has to be 5nf. use of cog capacitor material is recommended. the time measurement is triggered by the pwm or dir signal crossing the 50% level.
ATA6824C [datasheet] 9212g?auto?09/13 12 figure 4-6. timing of the drivers the delays t hxlh and t lxlh include the cross conduction time t cc . 4.10 short circuit detection to detect a short in h-bridge circuitry, internal comparat ors detect the voltage difference between source and drain of the external power nmos. if the transistors are switched on and the source-drain voltage difference is higher than the value v sc (4v with tolerances) the diagnosis pin dg1 will be set to ?h ? and the drivers will be switched o ff. all gate driver outputs (hx and lx) will be set to ?l?. releasing the gate driver output s will set dg1 back to ?l?. with the next transition on the pin pwm, the corresponding drivers, depending on the dir pin, will be switched on again. there is a pbat supervision block implemen ted to detect the possible voltage drop on pbat during a short circuit. if the voltage at pbat falls under v pbat_ok the drivers will be switched off and dg1 will be set to ?h?. it will be cleared as soon as the pbat undervoltage condition disappears. the detection of drain source voltage exceedances is activated after the short circuit blanking time t sc , the short circuit detection of pbat failure s operates immediately. t lxlh t lxr t hxlh t hxr t cc t hxhl t hxf t lxhl t lxf t cc hx lx pwm or dir 80% 50% 20% 80% 20% t t t
13 ATA6824C [datasheet] 9212g?auto?09/13 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . pin description pin name min max unit ground gnd 0 0 v power ground pgnd ?0.3 +0.3 v reverse protected battery voltage vbat +40 v reverse current out of pin vbat ?1 ma reverse protected battery voltage pbat +40 v reverse current out of pin pbat ?20 ma digital output /reset ?0.3 v vcc + 0.3 v digital output dg1, dg2, dg3 ?0.3 v vcc + 0.3 v 4.9v output, external blocking capacitor vint ?0.3 +5.5 v cross conduction time capacitor/resistor combination cc ?0.3 v vcc + 0.3 v digital input coming from microcontroller wd ?0.3 v vcc + 0.3 v watchdog timing resistor rwd ?0.3 v vcc + 0.3 v digital input direction control dir ?0.3 v vcc + 0.3 v digital input pwm control + test mode pwm ?0.3 v vcc + 0.3 v 5v regulator output vcc ?0.3 +5.5 v digital input vmode ?0.3 v vint + 0.3 v 12v output, external blocking capacitor vg +16 v digital output rx ?0.3 v vcc + 0.3 v digital input tx ?0.3 v vcc + 0.3 v serial interface data pin sio ?27 v vbat + 2 v source external high-side nmos s1, s2 (?2) +30 +40 (3) v gates external low-side nmos l1, l2 v pgnd ? 0.3 v vg + 0.3 v gates of external high-side nmos h1, h2 v sx ? 1 (2) v sx + 16 (2) v charge pump cplo v pbat + 0.3 v charge pump cphi v vres + 0.3 v charge pump output vres +40 (4) v switched vbat vbatsw ?0.3 v vbat + 0.3 v power dissipation p tot 1.4 (1) w storage temperature ? store ?55 +150 c reverse current cplo, cphi, vg, vres, sx ?2 ma lx, hx ?1 ma notes: 1. may be additionally limited by external thermal resistance 2. x = 1.2 3. t < 0.5s 4. load dump of t < 0.5s tolerated
ATA6824C [datasheet] 9212g?auto?09/13 14 6. thermal resistance parameters symbol value unit thermal resistance junction to heat slug r thjc <5 k/w thermal resistance junction to ambient when heat slug is soldered to pcb r thja 25 k/w 7. operating range the operating conditions define the limits fo r functional operation and parametric char acteristics of the device. functionality outside these limits is not implied un less otherwise stated explicitly. parameters symbol min max unit operating supply voltage (1) v vbat1 v thuv v thov v operating supply voltage (2) v vbat2 6 < v thuv v operating supply voltage (3) v vbat3 4.5 < 6 v operating supply voltage (4) v vbat4 0 < 4.5 v operating supply voltage (5) v vbat5 > v thov 40 v junction temperature range under bias t j ?40 +200 c normal functionality t a ?40 +150 c normal functionality, overtemperature warning set t j 165 195 c switch-off temperatures of drivers for h1, h2, l1, l2, sio and of vcc regulator t j 185 215 c notes: 1. full functionality 2. h-bridge drivers are switched off (undervoltage detection) 3. h-bridge drivers are switched off, 5v/3.3v regulat or with reduced parameters, reset works correctly 4. h-bridge drivers are switched off, 5v regulator not workin g, reset not correct 5. h-bridge drivers are switched off 8. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression iec-cispr25 level 5 esd (human body model) esd s 5.1 2kv cdm (charge device model) esd stm5.3. 500v note: 1. test pulse 5: v vbmax = 40v
15 ATA6824C [datasheet] 9212g?auto?09/13 9. electrical characteristics all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* 1 power supply and supervisor functions 1.1 current consumption v vbat v vbat = 13.5v (1) 25, 30 i vbat1 7 ma a 1.2 internal power supply 2 v int 4.8 4.94 5.1 v a 1.3 band gap voltage 3 v bg 1.235 v a 1.4 overvoltage threshold up v pbat 25 v thov_up 21.2 22.7 v a 1.4.1 overvoltage threshold down v pbat 25 v thov_down 19.7 21.3 v a 1.5 overvoltage threshold hysteresis v pbat 25 v tovhys 1 2.4 v a 1.6 undervoltage threshold up v vbat 30 v thuv_up 6.8 7.4 v a 1.6.1 undervoltage threshold down v vbat 30 v thuv_down 6.5 7.0 v a 1.7 undervoltage threshold hysteresis v vbat measured during qualification only 30 v tuvhys 0.2 0.6 v a 1.8 on resistance of v vbat switch v vbat = 13.5v 31 r on_vbatsw 100 ? a 1.9 undervoltage threshold pbat v vbat = 13.5v 25 v pbat_ok 6.1 7 v a 1.10 undervoltage threshold hysteresis pbat v vbat = 13.5v 25 v pbat_ok_hyst 0 100 mv a 2 5v/3.3v regulator 2.1 regulated output voltage 9v < v vbat < 40v, i load = 0ma to 100ma 29 v cc1 4.85 (3.2) 5.15 (3.4) v a 2.2 regulated output voltage 6v < v vbat 9v i load = 0ma to 100ma 29 v cc2 4.75 (3.2) 5.25 (3.4) v a 2.2a regulated output voltage 6v < v vbat 9v i load = 0ma to 80ma t a > 125c 29 v cc2 4.75 (3.2) 5.25 (3.4) v a 2.3 line regulation i load = 0ma to 100ma 29 dc line regulation <1 50 mv a * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
ATA6824C [datasheet] 9212g?auto?09/13 16 2.4 load regulation i load = 0ma to 100ma 29 dc load regulation <10 50 mv a 2.5 output current limitation v vbat > 6v 29 i os1 100 350 ma a 2.6 serial inductance to c vcc including pcb 29 esl 1 20 nh d 2.7 serial resistance to c vcc including pcb 29 esr 0 0.5 ? d 2.8 blocking cap at vcc (2), (3) 29 c vcc 1.1 3.3 f d 2.9 high threshold vmode 1 vmode h 4.0 v a 2.10 low threshold vmode 1 vmode l 0.7 v a 3 vg regulator 3.1 regulated output voltage v pbat 14v i max = 20ma 24 v vg 11 14 v a 3.2 regulated output voltage v pbat = 9v i max = 20ma 24 v vg 7.0 9.0 v a 4 reset and watchdog 4.1 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresh 4.8 (3.15) v a 4.1a tracking of reset thres-hold with regulated output voltage vmode = ?h? (vmode = ?l?) 29 v vcc1-vthresh 75 (50) mv a 4.2 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresl 4.3 (2.86) v a 4.3 hysteresis of /reset level vmode = ?h? (vmode = ?l?)(4) 29 hys resth 70 200 350 (240) mv a 4.4 length of pulse at /reset pin (5) 5 t res 7000 t 100 a 4.5 length of short pulse at /reset pin (5) 5 t resshort 200 t 100 a 4.6 wait for the first wd trigger (5) 5 t d 7000 t 100 a 4.7 time for vcc < v thresl before activating /reset (4) 29 t delayresl 0.5 2 s c 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
17 ATA6824C [datasheet] 9212g?auto?09/13 4.8 resistor defining internal bias currents for watchdog oscillator 3 r rwd 10 91 k ? d 4.9 watchdog oscillator period r rwd = 33k ? 3 t osc 11.09 13.55 s a 4.11 watchdog input low-voltage threshold 6 v ilwd 0.3 ? v vcc v a 4.12 watchdog input high-voltage threshold 6 v ihwd 0.7 ? v vcc v a 4.13 hysteresis of watchdog input voltage threshold 6 v hyswd 0.3 0.8 v a 4.14 close window (5) 6 t1 980 ?? t osc a 4.15 open window (5) 6 t2 780 ? t osc a 4.16 output low-voltage of /reset at i olres = 1ma 5 v olres 0.4 v a 4.17 internal pull-up resistor at pin /reset 5 r pures 5 10 15 k ? a 5 high voltage serial interface 5.1 low-level output current normal mode; v sio =0v, v rx =0.4v 13 il rx 2 ma a 5.2 high-level output current normal mode; v sio =v vbat v rx =v cc ?0.4v 13 ih rx 0.8 ma a 5.4 driver dominant voltage v busdom_drv_losup v vbat = 7.3v r load = 500 ? 8 v _losup 1.2 v a 5.5 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 500 ? 8 v _hisup 2 v a 5.6 driver dominant voltage v busdom_drv_losup v vbat = 7.3v r load = 1000 ? 8 v _losup_1k 0.6 v a 5.7 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 1000 ? 8 v _hisup_1k_ 0.8 v a 5.8 pull up resistor to vbat the serial diode is mandatory 8 r sio 20 30 60 k ? a 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
ATA6824C [datasheet] 9212g?auto?09/13 18 5.9 current limitation v sio = v bat_max 8 i sio_lim 40 250 ma a 5.9a current limitation in case of reset and sio overheat v sio = v bat_max reset = high 8 i sio_lim_reset 30 100 ma a 5.10 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v sio = 0v v vbat = 12v 8 i sio_pas_dom ?1 ma a 5.11 leakage current sio recessive driver off 8v < v vbat < 18v 8v < v sio < 18v v sio v vbat 8 i sio_pas_rec 30 a a 5.12 leakage current at ground loss control unit disconnected from ground loss of local ground must not affect communication in the residual network gnd device = v vbat v vbat =12v 0v < v sio < 18v 8 i sio_no_gnd ?1 1 ma a 5.13 node has to sustain the current that can flow under this condition. bus must remain operational under this condition v vbat disconnected v sup_device = gnd 0v < v sio < 18v 8 i sio 100 a a 5.14 center of receiver threshold v sio_cnt = (v th_dom +v th_rec )/2 8 v sio_cnt 0.475 ?? v vbat 0.5 ?? v vbat 0.525 ?? v vbat v a 5.15 receiver dominant state v en = 5v 8 v siodom 0.4 ?? v vbat v a 5.16 receiver recessive state v en = 5v 8 v siorec 0.6 ?? v vbat v a 5.17 receiver input hysteresis v hys = v th_rec ? v th_dom 8 v siohys 0.1 ?? v vbat 0.175 ?? v vbat v a 5.18 duty cycle 1 th rec(max) = 0.744 ? v vbat th dom(max) = 0.581 ? v vbat v vbat = 7v to 18v t bit = 50s d1 = t sio_rec(min) / 2 ? t bit (11) 8 d1 0.380 a 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
19 ATA6824C [datasheet] 9212g?auto?09/13 5.19 duty cycle 2 th rec(min) = 0.422 ? v vbat th dom(min) = 0.284 ? v vbat v vbat = 7v to 18v t bit = 50s d2 = t sio_rec(max) / 2 ? t bit (11) 8 d2 0.600 a 5.20 propagation delay of receiver t rec_pd = max(t rx_pdr ,t rx_pdf ) (11) 7v < v vbat < 18v 8 t rx_pd 6 s a 5.21 symmetry of receiver propagation delay t rx_sym = t rx_pdr ? t rx_pdf (11) 7v < v vbat < 18v 8 t rx_sym ?2 +2 s a 6 control inputs dir, pwm, wd, tx 6.1 input low-voltage threshold 10, 11, 6, 9 v il 0.3 ? v vcc v a 6.2 input high-voltage threshold 10, 11, 6, 9 v ih 0.7 ? v vcc v a 6.3 hysteresis 10, 11, 6, 9 hys 0.3 0.5 0.8 v a 6.4 pull-down resistor dir, pwm, wd, tx 10, 11, 6, 9 r pd 25 50 140 k ? a 6.5 rise/fall time 10, 11, 6, 9 t rf 100 ns a 7 charge pump 7.1 charge pump voltage load = 0a 21 vcp v vbat + v vg v a 7.2 charge pump voltage load = 3ma, c cp = 100nf 21 vcp v vbat + v vg ? 1 v a 7.3 period charge pump oscillator 21 t 100 9 11 s a 7.4 cp load current in vg without cp load load = 0a 21 i vgcpz 600 a a 7.5 cp load current in vg with cp load load = 3ma, c cp = 100nf 21 i vgcp 4 ma a 7.6 charge pump ok threshold up reference: pbat 21 v cpok_up 5.3 6.3 v a 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
ATA6824C [datasheet] 9212g?auto?09/13 20 7.7 charge pump ok threshold down reference: pbat 21 v cpok_down 4.5 5.5 v a 7.8 charge pump ok hysteresis 21 v cpok_hys 0.3 1.3 v a 8 h-bridge driver 8.1 low-side driver high output voltage 26, 27 v lxh v vg ? 0.5v v vg v a 8.2 on-resistance of sink stage of pins l1, l2 26, 27 r dson_lxl, x = 1, 2 25 ? a 8.3 on-resistance of source stage of pins l1, l2 26, 27 r dson_lxh, x = 1, 2 25 ? a 8.4 output peak current at pins l1, l2, switched to low v lx = 3v 26, 27 i lxl, x = 1, 2 100 ma a 8.5 output peak current at pins l1, l2, switched to high v lx = 3v 26, 27 i lxh, x = 1, 2 ?100 ma a 8.6 ohmic pull-down resistance at pins l1, l2 designed for 0v < v vbat <40v 26, 27 r pdlx x = 1, 2 25 140 k ? a 8.7 on-resistance of sink stage of pins h1, h2 v sx = 0 18, 20 r dson_hxl, x = 1, 2 25 ? a 8.8 on-resistance of source stage of pins h1, h2 v sx = v vbat 18, 20 r dson_hxh, x = 1, 2 25 ? a 8.9 output peak current at pins hx, switched to low v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxl, x = 1, 2 100 ma a 8.10 output peak current at pins hx, switched to high v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxh, x = 1, 2 ?100 ma a 8.11 static switch output low voltage at pins hx and lx v sx = 0v i hx = 1ma, i lx = 1ma 18, 20, 26, 27 v hxl , v lxl x = 1, 2 0.3 v a 8.12 static high-side switch output high-voltage pins h1, h2 i lx = ?10a (pwm = static) 18, 20 v hxhstat1 (7) v vbat + v vg ? 1 v vbat + v vg v a 8.13 ohmic sink resistance between pins hx and sx designed for 0v < v vbat <40v 17, 18, 19, 20 r pdhx 25 140 k ? a 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
21 ATA6824C [datasheet] 9212g?auto?09/13 dynamic parameters 8.15 propagation delay time, low-side driver from high to low figure 4-6 on page 12 v vbat = 13.5v 26, 27 t lxhl 0.5 s a 8.16 propagation delay time, low-side driver from low to high v vbat = 13.5v 26, 27 t lxlh 0.5 + t cc s a 8.17 fall time low-side driver v vbat = 13.5v c gx = 5nf 26, 27 t lxf 0.5 s a 8.18 rise time low-side driver v vbat = 13.5v 26, 27 t lxr 0.5 s a 8.19 propagation delay time, high-side driver from high to low figure 4-6 on page 12 v vbat = 13.5v 18, 20 t hxhl 0.5 s a 8.20 propagation delay time, high-side driver from low to high v vbat = 13.5v 18, 20 t hxlh 0.5 + t cc s a 8.21 fall time high-side driver v vbat = 13.5v, c gx = 5nf 18, 20 t hxf 0.5 s a 8.22 rise time high-side driver v vbat = 13.5v 18, 20 t hxr 0.5 s a 8.24 external resistor 4 r cc 5 k ? d 8.25 external capacitor 4 c cc 5 nf d 8.26 r on of t cc switching transistor 4 r oncc 200 ? a 8.27 cross conduction time (8) r cc = 10k ? c cc = 1nf 4 t cc 3.75 4.45 s a 8.28 short circuit detection voltage (9) 17, 19 v sc 3.5 4 4.7 v a 8.29 short circuit blanking time (10) 17, 19 t sc 5 10 15 s a 9 diagnostic outputs dg1, dg2, dg3 9.1 low level output current v dg = 0.4v (6) 14, 15, 16 il 2 ma a 9.2 high level output current v dg = vcc ? 0.4v (6) 14, 15, 16 ih 0.8 ma a 9. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 4.9.1 ?cross conduction time? on page 11 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 4-5 on page 9 ?definition of bus timing parameters?
ATA6824C [datasheet] 9212g?auto?09/13 22 11. package information 10. ordering information extended type number package remarks ATA6824C-mfhw tpqfp32, 7mm ? 7mm pb-free package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5157.01-4 1 11/25/08 package: epad tpqfp32 (acc. jedec outline) dimensions in mm specifications according to din technical drawings common dimensions (unit of measure = mm) min nom note max symbol a2 0.15 0.05 a1 3.5 bsc d2 3.5 bsc e2 0.3 0.45 0.37 b 0.45 0.75 0.6 l 0.8 bsc e 32 n 7 bsc e1 9 bsc e 7 bsc d1 9 bsc d 11.05 0.95 a2 1.2 a d d1 9 1 32 16 l e2 b 32 17 24 8 1 25 e1 e a d2 a1 e
23 ATA6824C [datasheet] 9212g?auto?09/13 12. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9212g-auto-09/13 ?? section 11 ?package information? on page 22 updated 9212f-auto-04/12 ?? section 5 ?absolute maximum ratings? on page 13 changed ?? section 9 ?electrical characteristics? number 4.1 on page 16 changed 9212e-auto-01/12 ?? qfn32 package variant on all pages removed 9212d-auto-11/11 ?? figure 5-5 ?definition of bus timing parameters? on page 9 changed ?? section 6 ?absolute maximum ratings? on page 13 changed ?? section 10 ?electrical characteristics? num bers 5.12, 5.14, 5.15, 5.16 and 5.17 on page 18 changed 9212c-auto-09/11 ?? section 5.1.2 ?voltage supervisor? on page 6 changed ?? section 5.5.2 ?pin pwm? on page 10 changed ?? section 10 ?electrical characteristics? num bers 1.4, 1.4.1 and 1.5 on page 15 changed 9212b-auto-04/11 ?? section 10 ?electrical characteristics? numbers 8.6 and 8.13 on page 20 changed
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